1. Technical Field of the Invention
The present invention generally relates to multiprocessor systems. More particularly, the present invention is directed to a system and method for evaluating a system of processors.
2. Description of Related Art
Without limiting the scope of the invention, the Background of the Invention is described in connection with systems of microprocessors, as an example. The functional verification of a system of microprocessors is concerned with ensuring a high degree of confidence in the functional quality and integrity of the system. More specifically, the functional verification of microprocessor systems includes extensive testing to diagnose any discrepancies between the design of the microprocessor system and intended functional behavior that affect the performance and electrical characterization of the microprocessor system.
Typically, a simulation-based verification tool, such as a manual or hand-coded test generation tool or a pseudo-random test generation tool, is employed to uncover errors by executing one or more test suites on the multiprocessor system and comparing the state of a particular processor under test (PUT) with an expected state after the test suites are applied.
In functional verification, an important metric to monitor is test coverage which is a measure of the completeness of the test suite with respect to a particular hardware platform. Following the execution of a test suite, data is analyzed to determine test coverage and to identify regions of the behavior of the processor system that are not well covered by the verification tool. Usually, verification engineers manually tune the verification tool or write a focused test sequence to supplement the gap in coverage. Typically, such tuning cannot be completely generated by software, but must instead be hand-coded by a verification engineer familiar with the target processor system. In addition to hand-coding the focused test sequence, the verification engineer must determine the proper expected state of the test sequence from the PUT.
In order to maximize test coverage and minimize the amount of manual tuning, a verification tool is sometimes employed in conjunction with ad hoc bus traffic code that is executed on each PUT. The bus traffic code increases the coverage of the verification tool by stressing the PUT and increasing the number of unique situations to which the processor is exposed.
A prior art system 100 for evaluating a multiprocessor platform 114 having multiple processors coupled via a system bus 124 is depicted in FIG. 1. A test generator 102 employing a verification tool such as pseudo-random test generation tool includes a test suite 104. Multiple test vectors operable with respect to the multiprocessor system 114, e.g., test vectors 106-112, are included in the test suite 104. The processor system 114 is exemplified with four microprocessors under test 116-122 coupled via the system bus 124. Each microprocessor is provided with specific bus traffic (BT) code that is integrated with its execution environment. As illustrated, BT 134 is included with processor 116, BT 134 is included with processor 116, BT 136 with processor 118, BT 138 with processor 120 and BT 140 with processor 122. Typically, the BT code is executed on the processors regardless whether a particular processor is executing any test code or not, in order to stress the operation of processors and thereby increase code coverage.
It has been found, however, that the existing schemes for evaluating multiprocessor systems are not without limitations. In particular, simultaneously maximizing coverage and throughput, that is, the number of test cases executed on a PUT during a specified period of time, has proved to be difficult. The code for creating bus traffic in order to maximize coverage monopolizes a PUT's computational time, and thus sacrifices throughput for test coverage.